Recently, Alphawave Semi announced the successful completion of the tape-out of the industry-leading UCIe IP subsystem on TSMC's N2 (2nm) advanced process node. The subsystem supports die-to-die transfer rates of up to 36G and is deeply integrated with TSMC's Chip-on-Wafer-on-Substrate (CoWoS) advanced packaging technology, significantly improving bandwidth density and scalability, laying the technical foundation for the next generation of chiplet architectures.
This breakthrough builds on Alphawave Semi's recent AI platform launches, further validating its capabilities in supporting disaggregated SoC architectures and hyperscale AI and high-performance computing (HPC) infrastructure. With this tapeout, Alphawave Semi is one of the first vendors to implement UCIe connectivity on 2nm transistor technology, marking a key step forward in the development of the open chiplet ecosystem.
Mohit Gupta, Senior Vice President and General Manager, Custom Silicon & IP, Alphawave Semi, said, "We are proud to be the first to bring UCIe IP into the 2nm era. This 36G subsystem validates a new high-density, low-power chiplet interconnection method, laying the foundation for future UCIe solutions with 64G and higher speeds, which is critical for AI computing and high-end network applications.”
Figure: Alphawave Semi completes tape-out of the UCIe IP subsystem on TSMC's 2nm process
The UCIe subsystem features a bandwidth density of 11.8 Tbps/mm, extremely low power consumption, excellent latency control, and support for real-time single-channel health monitoring and comprehensive testability. The solution is fully compliant with the UCIe 2.0 specification, compatible with multiple mainstream protocols including PCIe®, CXL™, AXI, CHI, etc., and integrates Alphawave Semi's highly configurable Streaming Protocol D2D controller to provide customers with flexible and efficient interconnection solutions.
As an active promoter of the open chiplet ecosystem, Alphawave Semi is deepening cooperation with industry partners to jointly promote open technology standards based on D2D interconnection and accelerate the implementation and evolution of AI connected platforms. In the era of chipping, Alphawave Semi is playing a key role in building a more scalable, interoperable underlying foundation for the global AI and HPC markets.
Yuan Lipen, Senior Director of Advanced Technology Business Development at TSMC, also said, "Our partnership with Alphawave Semi reaffirms our commitment to jointly advancing high-performance computing. "By leveraging TSMC's advanced process and packaging strengths, combined with the Open Innovation Platform® (OIP) ecosystem, we are able to accelerate the delivery of custom silicon and advanced interface IP for AI and cloud infrastructure."
At present, Alphawave Semi has begun to lay out the next generation of UCIe solutions, and plans to launch products that support 64G speeds, helping AI and HPC customers continue to lead in the wave of chiplet-driven technological innovation. As the technology of the 2nm node matures, the importance of UCIe as a unified chip-to-die interconnection standard is becoming more and more prominent, and Alphawave Semi is undoubtedly injecting key impetus into the development of this ecosystem.
