As the demand for AI computing reshapes the semiconductor market, Arteris recently announced a comprehensive upgrade of its multi-chip solution, further consolidating its technology foundation in the chip era, and providing a faster and more flexible innovation path for global chip design.
"In the new era of die architecture, the computing power provided by traditional single-chip designs can no longer meet the rapidly growing computing demand," said K. Charles Janac, President and CEO of Arteris.”
The Rise of Chip Architecture: From Moore's Law to System Innovation
With the slowdown of Moore's Law, it is difficult for the chip manufacturing process to achieve a performance leap by increasing transistor density alone, especially in highly compute-intensive fields such as AI and big data, and the innovation of system architecture is particularly critical. The multi-core system came into being, which has become a new way to improve computing power and energy efficiency. Arteris' expanded multi-die platform is a cutting-edge technology portfolio that accelerates the time from design to silicon while balancing high-performance computing and automotive-grade reliability.
From technological innovation to commercial implementation: accelerate the path of industrial transformation
Based on its core network-on-chip (NoC) technology, Arteris' new solution optimizes the chip-chip and SoC design flow to help developers address power, performance, and area (PPA) bottlenecks. The solution supports standardized chip-to-die interconnect interfaces, is compatible with mainstream protocols such as UCIe, Arm AMBA, and PCIe, and integrates the ecological resources of leading EDA tool vendors and fabs to ensure that the solution has good deployability and system compatibility.
Highlights of core technical capabilities:
FlexNoC Non-Conformance IP: Proven in silicon, supporting mainstream standards, and compatible with mainstream chip controllers and PHY interfaces on the market.
Ncore Consistent NoC Extension: Implements cache coherent access across chips, making the entire system behave like a single chip at the software level.
Magillem Connectivity Automation: Simplify SoC integration from IP to chip, reducing project risk associated with manual integration.
Magillem Register Automation: Connect the entire process from system definition to software validation, and build a "single source of truth" hardware and software collaboration environment.
Figure: Arteris Accelerates the Chiplet Era: Building a New Ecosystem for AI and Automotive Chips
Multi-party collaboration: Jointly create a core grain ecological map
To better support the next generation of AI and automotive platforms, Arteris is working with key partners across the semiconductor value chain to co-innovate:
Arm: Jointly promote the AMBA CHI C2C standard, facilitate the interconnection of the chip ecosystem, and serve both mutual automotive customers and OEMs.
Cadence: Provides a portfolio of EDA tools and IP that is deeply integrated with Arteris to dramatically reduce time-to-market for chip products.
Renesas: Its fifth-generation R-Car SoC platform uses Arteris technology, combined with CPU, NPU, GPU, and chip expansion capabilities to drive ADAS systems to higher AI computing power.
RISC-V camp (e.g., Andes, SiFive, Tenstorrent): Extensive cooperation with Arteris on domain-specific IP and chip cooperation.
Synopsys: Partnering with Arteris to drive rapid, prescriptive multi-die integrated designs by standardizing UCIe IP and EDA platforms.
A number of industry executives also expressed their high recognition of this cooperation:
David Glasco, vice president of R&D at Cadence, said, "As AI continues to escalate its challenges to both computing power and energy efficiency, chiplet architecture is becoming key to next-generation SoCs. The cooperation with Arteris is not only to accelerate the advent of the core era, but also to jointly build a future ecosystem. ”
Aish Dubey, General Manager of Renesas' HPC SoC business, said, "Arteris technology has played an irreplaceable role in on-chip connectivity in achieving the goal of high integration and high scalability of the R-Car Gen5 platform."
Ian Ferguson, Vice President of SiFive, emphasized: "We have a long-standing relationship with Arteris and are committed to helping our customers reduce development risks and costs. The launch of the multi-core solution is a natural extension of the cooperation between the two parties.”
"The deep synergy between Synopsys UCIe IP and Arteris NoC enables developers to accurately model early in the architecture phase and drive rapid development of complex core systems," said Neeraj Paliwal, senior vice president of product management at Synopsys."
Dr. Debendra Das Sharma, President of the UCIe Alliance, concluded: "Arteris' innovation is the cornerstone of the open and scalable die standard."
