On February 26, 2025, Arteris, Inc., which specializes in delivering system IP to accelerate system-on-chip (SoC) creation, announced that the next generation of Magillem Registers technology for SoC integration automation is now generally available. This product is revolutionizing the semiconductor design world, reshaping the SoC development workflow and driving efficiency in the industry.
In today's semiconductor industry, SoC designs are becoming more and more complex, and the vigorous development of technologies such as artificial intelligence and the Internet of Things (IoT) has led to more and more functions integrated by chips, and the scale is getting larger and larger. According to industry data, more than 70% of chips currently require respins, which not only increases development costs, but also extends the time-to-market. Against this backdrop, how to efficiently integrate hardware and software has become a major challenge for many SoC design teams. This challenge has become even more acute, especially with the widespread use of AI logic in chips, which have become increasingly complex and size-in-class.
Arteris' Magillem Registers is a full-featured register design and management product that enables precise automation of hardware/software interfaces (HSIs) for rapid development of everything from small chips for IoT devices to complex multi-chip SoCs for AI data centers. For chip architects, hardware designers, firmware engineers, verification teams, and documentation teams, it serves as a collaborative bridge to help them break down communication barriers and overcome the complexities of the design process. With a unified specification and compilation process, Magillem Registers can effectively avoid the risk of outdated standards and ensure the accuracy of their designs.
This product is an upgrade from the silicon-proven Magillem 5 and CSRCompiler technologies. It provides an integrated, single source of truth infrastructure for specifying, documenting, implementing, and verifying SoC address mappings, streamlining and streamlining workflows. In this process, efficient IP reuse is greatly facilitated, and data consistency between different design teams is ensured. With more than 1,000 semantic and syntax checks, Magillem Registers ensure high-quality output and significantly reduce the risk of chip failure, whether it's third-party IP, in-house developed IP, or verification of entire system integration. In addition, intelligent automation reduces HSI development time by 35% compared to manual operations, allowing development teams to cope with tight project deadlines.
figure:Arteris Releases the Latest Generation of Magillem Registers to Automate Semiconductor Hardware Software Integration
The new generation of Magillem Registers delivers major breakthroughs in performance, capacity, standard support, and ease of use. With nearly 3x faster performance than Magillem 5, millions of registers can be compiled in minutes and synthesizable RTL register banks are automatically generated. It supports a 5x larger design scale, seamlessly adapting to development needs ranging from small devices to large multi-chip devices with millions of control registers.
In terms of standards support, Magillem Registers adds support for industry standards such as IEEE 1685 - 2022 (IP - XACT) and SystemRDL 2.0, in addition to being compatible with previous versions. This improvement further enhances intellectual property (IP) reusability, expands compatibility with third-party IP vendors, and facilitates SoC integration. In terms of ease of use, the product creates a fast, highly iterative design environment with features such as simplified input, intuitive document navigation, customizable workflows, and advanced automation technology that eliminates repetitive, time-consuming, and error-prone manual tasks, dramatically improving team productivity, and meeting the growing demands of the modern design environment with unmatched efficiency and scalability.
K. Charles Janac, President and CEO of Arteris, Inc., said, "Today, the complexity of chip designs continues to rise, with more than 70% of chips requiring redesign, putting tremendous pressure on SoC design teams. AI SoCs and FPGAs are expensive and time-consuming to develop, and automation efficiency is critical to cost control. We're releasing the next generation of Magillem Registers, designed to maximize productivity in SoC engineering and significantly reduce project risk.”
Arteris' SoC integrated automation product line, including the launch of Magillem Registers, is designed to address design complexity through automation, unleash team productivity, and accelerate the design flow of high-quality chips and SoCs, breathing new life into the semiconductor industry and driving the industry toward a more efficient and intelligent direction.
