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Intel Unveils Next-Generation 18A Wafer Technology: Improved Performance, Lower Power Consumption, and Higher Density

Intel detailed the advantages of its 18A manufacturing technology (1.8nm class) over Intel's 3 process at the VLSI Symposium. As expected, the new process nodes will deliver significant improvements in power, performance, and area (PPA) metrics, providing tangible benefits for client and data center products.

Ⅰ The PPA index has been significantly improved

The PPA index is the core evaluation standard used by the semiconductor industry to measure the process performance of the chip manufacturing process, representing three key dimensions: performance, power consumption, and area. These three indicators are interrelated and affect each other, which together determine the comprehensive competitiveness of chips, and are also the core goals of chip designers and foundries to optimize process technology. Intel claims a 25% performance improvement in 18A process technology at the same voltage (1.1V) and complexity compared to the same modules built on Intel 3 process technology. For standard Arm core submodules, power consumption is reduced by 36% at the same frequency and 1.1V. At lower voltages (0.75V), 18A delivers an 18% increase in performance and a 38% reduction in power consumption. In addition, the 18A always achieves 0.72x area scaling compared to Intel 3.

Ⅱ Key technologies: GAA transistors and PowerVia backside power supply network

Intel's 18A manufacturing technology is the company's first node to rely on a full-surround gate (GAA) RibbonFET transistor and a PowerVia backside power delivery network (BSPDN), both of which deliver major PPA benefits.

As can be seen from a comparison of standard cell layouts, 18A achieves significant physical scaling compared to Intel 3 in both high-performance (HP) and high-density (HD) libraries. In the HP library, the 18A reduces the unit height from 240CH to 180CH; In the HD library, from 210CH to 160CH, the vertical size is reduced by about 25%. This more compact cell architecture allows for increased transistor density, which directly contributes to area efficiency.

The use of PowerVia BSPDN enables more efficient vertical routing by offloading power cables from the front of the IC, freeing up space for signal routing and further compressing the layout. In addition, the improved gate, source/drain, and contact structures improve overall cell uniformity and integration density. Together, these enhancements enable the 18A to deliver better performance per unit area and energy efficiency, enabling more advanced and compact chip designs.

Figure: Intel Reveals Next-Generation 18A Wafer Technology: Dramatically Improved Performance, Lower Power Consumption, and Higher Density

Figure: Intel Reveals Next-Generation 18A Wafer Technology: Dramatically Improved Performance, Lower Power Consumption, and Higher Density

Ⅲ Cooperate with a third party in the production plan

Intel is reportedly expected to begin mass production of compute chiplets codenamed Panther Lake processors for client PCs later this year, followed by early 2026 production of chiplets for Clearwater Forest data center systems. In addition, the company is on track to complete the tape-out of the first 18A-based third-party designs by mid-2025.

Clearly, there is interest in developing third-party chips based on 18A. In addition to submitting a generic paper describing its 18A technology, Intel plans to submit a paper describing a PAM-4 transmitter implemented using 18A process nodes and BSPDN, co-authored by engineers from Intel, Alphawave Semi (a contract chip designer and IP vendor), Apple, and NVIDIA. This doesn't necessarily mean that Apple or Nvidia will use the 18A for the production of chips, but it at least shows that they are interested in conducting research.

Ⅳ Competition and challenges with TSMC's N2 process

Speaking of Apple and Nvidia, TSMC said that almost all partners plan to adopt its N2 (2nm-class) process technology, so it is reasonable to expect that the node will be more widely adopted than Intel's 18A. Still, the key for Intel is to prove that it can develop competitive nodes and mass produce them, so 18A will play a vital role in the future of Intel's foundry business.

Another key question is what happens when the PowerVia/BSPDN is removed. I've heard that the technology adds a considerable amount of cost, so it's likely that some customers will choose to forgo it. So, how competitive is an 18A without the technology? How does the 18A with this technology compare to TSMC's process cost? It may take a while for these questions to be answered.

At the moment, Intel is even avoiding adopting more products on the Intel 3 process, presumably in order to shift resources to 18A. With the advancement of 18A process technology, it is worth continuing to see if Intel can regain competitiveness in the advanced process field.

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