Rapidus Corporation, a manufacturer of advanced logic semiconductors, today announced that it has entered into an agreement with Synopsys Inc., a provider of system design solutions, to significantly shorten the design cycle with a revolutionary new approach to help simulate process sensitivities and variations locally during the design phase. This innovative approach significantly reduces the costly library and memory recharacterization required at different stages of the process evolution, thereby reducing design iterations and speeding up the execution of the overall project.
Breakthrough design processes for process optimization
Under the agreement, Synopsys will leverage its AI-driven EDA (Electronic Design Automation) suite to help Rapidus develop advanced design flows and offer a broad portfolio of IP (intellectual property) on Rapidus' 2nm Full Gate (GAA) process. This collaboration will advance Rapidus' Design for Manufacturing and Co-Optimization (DMCO) design concept, enabling simultaneous design and manufacturing optimization and accelerating the design process.
Solve semiconductor design cycle bottlenecks
In traditional semiconductor design, the IP needs to be recharacterized every time a process design kit (PDK) or manufacturing process is updated, which often becomes a bottleneck in the design cycle. It can take two to three months to generate a timing model, which significantly slows down the design schedule. This problem was solved by adopting Synopsys' AI-driven EDA products, specifically its machine learning (ML)-based time series model generation tool, PrimeShield™. PrimeShield™ dramatically accelerates timing model generation by rapidly generating sensitivity libraries every time a PDK or manufacturing process is updated. Combined with Rapidus' rapid manufacturing process wafer data, this approach not only improves the accuracy of the model, but also accelerates the design convergence process.
Figure: Rapidus partners with Synopsys to accelerate design optimization for 2nm GAA processes
Collaborative optimization driven by AI and big data
Synopsys' AI-driven EDA process will drive the convergence of design for manufacturing (MFD) and design for manufacturing (DFM) concepts by combining Rapidus' big data. Rapidus will use sensors and AI in its processes, streamlining the design process and optimizing based on big data from silicon wafers during the manufacturing process. This collaboration will enable Rapidus to improve manufacturing quality and efficiency through more accurate design decisions, providing customers with higher production yields.
Enhance market competitiveness and accelerate product launch
Rapidus is working to improve its competitiveness in the market by building its Rapid Unified Manufacturing Service (RUMS). RUMS aims to reduce the overall time to market for customers by providing integrated design support and front-end and back-end processes. "Through the collaboration with Synopsys, Rapidus will further strengthen its design support capabilities, advance DMCO design concepts, and shorten product development cycles."
"Our collaboration with Synopsys is an important milestone in accelerating our design process," said Dr. Koike, CEO of Rapidus. Rapidus' vision is to use a single-wafer front-end process to fully exploit the big data generated by that process. "The high compatibility with Synopsys' AI-driven EDA processes and IP will enable us to achieve our production goals faster than anywhere else."
Conclusion
This collaboration will enable Rapidus to achieve a significant breakthrough in the design optimization of the 2nm GAA process, not only accelerating the design cycle, but also providing powerful data support for future manufacturing processes. "With Synopsys' advanced EDA tools and AI technology, Rapidus will be able to more effectively leverage big data to drive simultaneous optimization of semiconductor design and manufacturing, providing customers with more efficient and reliable products."
