At the Intel Foundry Technology Conference, Synopsys announced a number of strategic collaborations with Intel Foundry to collaborate on advanced process EDA tools, chip interconnect technologies, and IP core development to drive breakthroughs in AI and high-performance computing chips.
The 18A process technology is fully ready
Synopsys' AI-driven digital and analog design flow is certified on Intel's 18A process, and its EDA toolchain is production-ready for 18A-P nodes with RibbonFET surround gate transistors and PowerVia backside power. Through deep optimization, the Synopsys toolchain leverages the performance benefits of Intel's PowerVia power network for thermal-aware design optimization. The long-term design process co-optimization (DTCO) by the engineering teams of both companies enables designers to achieve better power, performance, and area performance on the 18A series nodes.
Currently, the two companies have started early technology adaptation for the next generation of 14A-E nodes to prepare for future process upgrades.
Breakthroughs in advanced packaging technology
In the heterogeneous integration space, the Synopsys 3DIC Compiler platform will provide full-flow design support for Intel's EMIB-T silicon bridge packaging technology. This innovative packaging solution combines the technical advantages of EMIB 2.5D and Foveros 3D to enable high-density interconnects of very large chips. Synopsys' unified design platform supports the entire process from early bump planning to final signoff, automating UCIe and HBM cabling, dramatically improving design efficiency for 3D heterogeneous integration.
Figure: Synopsys and Intel Foundry Deepen Collaboration to Revolutionize AI Chip Design
Build a complete IP ecosystem
To meet the extreme performance and power requirements of AI and HPC chips, Synopsys is developing the industry's most comprehensive IP portfolio, including IP cores that support high-speed interfaces such as 224G Ethernet and PCIe 7.0, as well as foundational IP such as embedded storage and logic libraries. These IPs will take full advantage of Intel's PowerVia technology to provide more efficient power distribution for chip designs.
Jointly build an industrial innovation ecosystem
As a new member of the Intel Foundry Accelerator Alliance, Synopsys will participate in the Design Services Alliance and the Chiplet Alliance. "By providing optimized EDA tools, IP and design services, Synopsys will enable customers to accelerate the development of complex chips based on Intel's 18A process." In the chiplet space in particular, Synopsys will drive standards for interoperability and manufacturability of multi-chip designs.
"Our collaboration with Intel is redefining the silicon-to-system design approach to deliver a complete solution to the needs of the AI era," said John Koeter, senior vice president of the IP Group at Synopsys. "By combining Intel's system-level foundry capabilities with Synopsys' design tools, customers can innovate faster with differentiation," said Suk Lee, vice president of technology for Intel's foundry ecosystem. "
This cooperation marks the comprehensive collaboration of the two companies in advanced processes, packaging technologies and design ecosystems, and will provide key technical support to cope with the explosive growth of AI computing.
