Synopsys today announced that it is deepening its strategic collaboration with Samsung Foundry to advance advanced chip designs for next-generation edge AI, high-performance computing (HPC) and artificial intelligence (AI) applications. "The collaboration combines Synopsys' 3DIC Compiler platform with Samsung's advanced packaging technology to enable customers to efficiently tape-out complex chips and significantly shorten development cycles."
The certified EDA design flow built on Samsung's SF2P process node enables customers to achieve significant improvements in power, performance, and area (PPA) optimization, as well as the ability to integrate high-quality IP portfolios on advanced processes to reduce system integration risk.
"The widespread adoption of AI at the edge is creating an urgent need for more robust and efficient semiconductor technologies." "Our close collaboration with Samsung's foundry is enabling high-performance AI processors built on Samsung's advanced processes, especially sub-2nm, in applications ranging from data center AI inference engines to lightweight end devices such as smart cameras and drones."
Hyung-Ock Kim, Vice President of Foundry Design Technology at Samsung Electronics, added, "We are working with Synopsys to optimize the PPA performance of our designs under Samsung's advanced processes. Synopsys' AI-driven design flow is certified for SF2 and SF2P processes, allowing customers to easily integrate it into their existing development stacks. In addition, we continue to push the boundaries of innovation in multi-die system design with our joint 2.5D packaging solutions, including the I-CubeS, and automated placement and routing capabilities with the help of 3DIC Compiler.”
The cooperation in the field of multi-grain design has achieved remarkable results
In the area of multi-die packaging, the two companies have achieved important milestones. A customer silicon design based on Synopsys' 3DIC Compiler and Samsung's I-CubeS 2.5D packaging technology was successfully taped out. The technology supports the integration of multiple HBM stacked chips on a silicon interposer, enabling high-speed HBM routing in just 4 hours with the Synopsys 3DIC Compiler while increasing the worst-case eye opening by 6%, enhancing overall system performance and reliability.
The 3DIC Compiler has been certified for Samsung's X-Cube advanced packaging process, from 3D floor planning to Bump/TSV cabling and early thermal analysis, providing solid support for the subsequent large-scale 3D system development.
Figure: Synopsys partners with Samsung foundry to accelerate the implementation of advanced AI, HPC, and edge intelligent chip designs
Design Technology Collaborative Optimization (DTCO) and EDA process collaborative upgrade
Building on Synopsys' decades-long collaboration with Samsung, we are advancing AI-based design-based co-optimization (DTCO) to unlock the PPA potential of SF2 and SF2P processes. In addition, the two companies have also worked together to create a new schematic migration path to efficiently migrate Samsung's SF4 analogue IP to SF2 nodes.
In the digital and analog design space, Synopsys' AI-driven EDA toolchain (Synopsys.ai) is also SF2P certified, including digital circuit design optimized by hypercells (high-efficiency cells) that make standard cells more compact to use, further improving PPA performance. Both analog and digital processes on the SF2 and SF2P nodes are certified, accelerating SoC differentiation for customers at advanced process nodes.
Rich IP portfolio accelerates time-to-market
Synopsys and Samsung are strategically working together on the IP ecosystem to provide chip designers with high-quality IP support across the entire process node, from 14LPP, 8LPU, and SF5A to SF4X and SF2P/A, serving multiple markets such as high-performance computing, mobile devices, consumer electronics, IoT, and automotive.
Synopsys IP covers:
1. High speed interface IP: 224G、UCIe、PCIe 7.0、MIPI、LPDDR6X and USB4;
2. Basic IP: e.g. embedded memory, logic library, general-purpose IO (GPIO), voltage/process/temperature (PVT) sensors;
3. Security & Chip Lifecycle Management IP (SLM).
"With its low-risk, high-confidence IP products deeply integrated with Samsung's processes, Synopsys helps customers accelerate high-end chip development, shorten time-to-market, and enhance product competitiveness."
This in-depth collaboration not only strengthens the core position of both parties in the AI and high-performance computing chip ecosystem, but also provides a more efficient and advanced design and development path for global chip design companies.
